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Virtex-5 LX110 FPGA PMC module


The PMC-FPGA05 is a Xilinx Virtex-5 XC5VLX110 platform FPGA based, PMC module with high speed digital I/O and PCI-X interface to the host computer. The PMC-FPGA05 is aimed at embedded application development.

Block Diagram


 Block Diagram


PMC-FPGA05 Block diagramXilinx Virtex-5 FPGA

The Virtex-5 XC5VLX110 FPGA is configured from FLASH. A default image which instantiates the PCI-X interface and Flash programming interface is preloaded into the FLASH along with a recovery image which cannot be overwritten. There is space for 3 or more configurations and the image used is selected by switch.

Digital I/O

There are 138 signals routed to a 180-way connector near the front panel. These lines are routed so that they may be used as single-ended signals or differential pairs. The FPGA I/O signals are banked, with two banks being used at the front panel connector. Each bank is independently configurable to 2.5V or 3.3V signalling.

Developers can create custom modules suited to their application as VMETRO supply complete specifications for these modules with the documentation that comes with the board.

Another bank of 64 single-ended lines (32 differential pairs) connects to P14, the PMC user I/O connector, to support rear I/O.


By default, three banks of 2Mb x 18 (4Mbytes) QDR II SRAM supports DSP functions in the Virtex-5 and is directly connected to the FPGA. Larger SRAM devices are supported; contact VMETRO for availability. Each QDR II SRAM is clocked at 200MHz, allowing for simultaneous read and write operations each at 800Mbytes/s for a board aggregate of 4800Mbytes/s.

Two independent banks of 512Mb x 16 (64-Mbytes) DDR2 SDRAM are directly connected to the FPGA by default. Larger memories are supported; contact VMETRO for availability. Clocked at 200MHz, each bank can be used completely independently (e.g. filling one memory while emptying data from the other at 800Mbytes/s) or as a single 32-bit wide, 1600Mbytes/s memory structure. This memory is accessible from the PCI-X bus and provides a large pool of memory to buffer DMA transfers and other large data block operations. 


The FLASH is a 256Mbit (32Mbytes) device used to store product description data and the images used to configure the Virtex-5 FPGA. The FLASH is programmable via a PCI register that maps LSB of the PCI-X bus to the FLASH bus. The default image provides the PCI-X interface and access to the Flash for programming. A recovery image is also provided that cannot be overwritten.


The PMC-FPGA05 is initially supported under the Windows XP operating system, with VxWorks and Linux to follow (Contact VMETRO for availability). The BSP includes:

VHDL library code blocks (demonstrating how board resources can be used) Windows XP drivers
API with C support libraries
Example code
FLASH programming and board debug utilities
Hardware and software manuals

Development of VHDL code for the FPGA requires synthesis tools such as Xilinx Foundation.

« December 2018 »